Biden Administration Announces Research and Development Program to Accelerate Semiconductor Advanced Packaging

The National Advanced Packaging and Manufacturing Program
In 2022, the CHIPS and Science Act allotted over $50 billion to the CHIPS for America program, administered by the Department of Commerce, to empower U.S. leadership in semiconductor manufacturing and design. Of that funding, $39 billion was designated to broaden the capacity of the U.S. to manufacture semiconductors and $11 billion to propel U.S. leadership in semiconductor R&D, which includes funding to support the National Advanced Packaging and Manufacturing Program (NAPMP).

NAPMP, as noted in our earlier alert on the topic, is designed to onshore advanced packaging facilities and capabilities, by providing adequate technology and supplying the packaging workforce with the necessary skillsets for a robust packaging industry. NAPMP sets out to create a self-sufficient, yet profitable, domestic packaging industry that will meet the demand of domestic chip makers for packaging that will result from the CHIPS and Science Act investments in domestic manufacturing.

Funding Opportunity Structure
The NOFO provides an opportunity for eligible applicants to apply to fund projects that will advance one of five technical R&D areas. The NOFO anticipates awarding a varying amount of funding to each applicant and providing a varying total of funding available under each research area with $50 million reserved for prototyping activities. The performance period of each award is five years.

Details on the five research areas, their allocated funding levels, and the size of the awards to be issued under that research area are below:

I. Equipment, Tools, Processes and Process Integration

• Purpose: The goal of this R&D area is to create and distribute advanced tools and processes. Applications under this R&D area must include one or both of the following sub-areas: process cluster development and end-to-end advanced packaging flows. Projects should also provide training and educational opportunities for the packaging workforce. An ideal proposal addresses the packaging equipment needed for advanced processing, which can then be disseminated to a developing advanced packaging workforce.
• Funding: $450 million is allocated in total to this research area, with individual awards of up to $150 million.

II. Power Delivery and Thermal Management

• Purpose: The Power Delivery and Thermal Management R&D area seeks to address challenges regarding power delivery, power efficiency and thermal management for advanced packaging. Overcoming these challenges is essential to enhance the speed and efficiency of semiconductor-based systems. Applications should focus on improving the efficiency of semiconductor systems through advancement in power delivery and thermal management.
• Funding: $250 million is allocated in total to this research area, with individual awards of up to $50 million.

III. Connector Technology, Including Photonics and Radio Frequency (RF)

• Purpose: This R&D area seeks to develop innovation for “high data-rate, low latency, small footprint, error-free, and energy efficient connections between packaged sub48 assemblies.” Selected proposals will foster connectors that include computational capability, data preprocessing and security, as well as simple installation to the packaged assembly.
• Funding: $250 million is allocated in total to this research area, with individual wards of up to $100 million.

IV. Chiplets Ecosystem

• Purpose: This area seeks to enhance key aspects of advanced packaging such as wire abundance, ultra-large packages and heterogeneous integration to achieve the objectives of the program. A goal of the NAPMP is to seek a level of integration that “blurs the line between chip and package.” Through the Chiplets Ecosystem R&D area, chiplets will influence advanced technology in high-volume manufacturing.
• Funding: $300 million is allocated in total to this research area, with individual awards of up to $75 million.

V. Co-Design/Electronic Design Automation (EDA)

• Purpose: This R&D area seeks to create an innovative layer of abstraction to scale-out advanced package designs made up of systems of chiplets. Creating this layer of abstraction along with tools that will develop a full end-to-end co-design and EDA solution for advanced packaging as an essential part of the overall semiconductor design stack is the ideal outcome for this R&D area. Applicants can expect to collaborate with other project teams by providing tools and support for other NAPMP-funded projects.
• Funding: $250 million is allocated in total to this research area, with individual awards of up to $100 million.

It should be noted that there is no federal cost share requirement or limitation under this NOFO. Some projects may be able to receive awards for the entire project. However, the Department of Commerce will prioritize applications that can share costs with the government. Such applications may be more successful as they would allow for the government to issue more awards to more projects and further accelerate towards NAPMP goals.

Eligible Applicants
A broad range of applicants are eligible for the CHIPS R&D funding. Overall, projects should be informative for the future of the manufacturing and packaging workforce and promote the creation of a self-sufficient U.S. semiconductor system. Eligible applicants include domestic nonprofit and for-profit organizations, domestic higher education institutions, as well as state and local tribal governments. Project proposals that include cross collaboration within the manufacturing and supply chain as well as proposals including academic and nonprofit sectors are specifically encouraged.

Companies with foreign ownership will want to review any potential connections to foreign adversaries before applying. As with other CHIPS Act programs, Foreign Entities of Concern (FEOCs) are ineligible to receive funding. A company will be considered an FEOC if it is “owned by, controlled by, or subject to the jurisdiction or direction of a government” of a foreign adversary. This will be met where a company is organized under the laws of the adversarial country, has its principal place of business in the adversarial country, has 25% or more of its ownership held (directly or indirectly) by the government of a foreign country, or has 25% or more of its interest held (directly or indirectly) by a national who is currently located in the adversarial country, a company located or organized in the adversarial country, or a company who has 25% of its interest held by an adversarial government. Listed adversarial countries are North Korea, China, Russia and Iran.

Application Process
This application process proceeds in two phases: first, submission of concept papers and second, the selection and invitation of certain applicants to submit full applications. Concept papers can be submitted now and are due by December 20, 2024. Applicants are limited to one concept paper per R&D area, however, separate concept papers on different R&D areas may be submitted. Proposals and concept papers should include milestones that demonstrate measurable steps for the project. The CHIPS Research and Development office held a Proposers Day on October 22 which provided further details about each R&D area.

Once concept papers are evaluated, the CHIPS R&D office will invite certain applicants to provide full applications. Selected applicants will have 60 days to finalize their full application upon receipt of selection from the office. Invited applicants are expected to be selected on February 24, 2025—with full applications then due by April 25, 2025. Final awards may then be expected to be announced in late 2025.